Radio frequency (RF) switches are one of the highest volume RF devices used in wireless systems. In recent years, complementary metal-oxide semiconductor (CMOS) on silicon-on-insulator (SOI) substrate has become a major technology in the manufacturing of the RF switches. Fabrications of the RF CMOS switches on the SOI substrates may benefit from low cost, a large scale capacity of wafer production, and well-established CMOS libraries and design tools.
The RF CMOS switches fabricated on conventional SOI substrates, however, bear deleterious back-gate transistors, which affect isolation performance of the RF CMOS switches. The conventional SOI substrate 10 shown in FIG. 1 includes a silicon handle layer 12, a silicon oxide layer 14 over the silicon handle layer 12, and a silicon epitaxy layer 16 over the silicon oxide layer 14.
After the conventional SOI substrate 10 is formed, electronic components including RF CMOS switches may be integrated in or on the silicon epitaxy layer 16 to form a device layer 18 as depicted in FIG. 2. The device layer 18 may have a different thickness from the silicon epitaxy layer 16.
FIG. 3 shows an exemplary RF CMOS switch 20 residing in the device layer 18 within section A of FIG. 2. The exemplary RF CMOS switch 20 includes a source 22, a drain 24, a body 26, a gate dielectric region 28, a gate 30, a source contact 32, a drain contact 34, and a gate contact 36. In detail, the source 22, the drain 24, and the body 26 are formed over the silicon oxide layer 14. The gate dielectric region 28 is formed over the body 26, and the gate 30 is formed over the gate dielectric region 28. For simplification, other necessary regions of the RF CMOS switch 20 such as Field Oxide, Gate Spacers, and Metal layers are not depicted.
Herein, the source 22, the drain 24, the body 26, the gate dielectric region 28, and the gate 30 are used to achieve an intentional front-gate switch function of the exemplary RF CMOS switch 20. An upper solid arrow from the source 22 to the drain 24 shows a first conducting channel which operates when the intentional front-gate switch function of the exemplary RF CMOS switch 20 is enabled. Meanwhile, the source 22, the drain 24, the body 26, the silicon oxide layer 14, and the silicon handle layer 12 form an undesired back-gate transistor, where the silicon oxide layer 14 is used as a gate dielectric region in the back-gate transistor and the silicon handle layer 12 is used as a gate in the back-gate transistor. The front-gate switch and the back-gate transistor share the common source 22, the common drain 24, and the common body 26. A lower dashed arrow from the source 22 to the drain 24 shows a second conducting channel when the back-gate transistor operates in a closed mode.
FIG. 4 shows a drain-to-source current of the back-gate transistor in the RF CMOS switch 20 that is fabricated on the conventional SOI substrate 10 using typical commercial RF SOI technologies. The drain-to-source current is measured as a function of a back-gate voltage (a voltage applied to the silicon handle layer 12) when a front-gate voltage (a voltage applied to the gate 30) is off. For this RF SOI technology, the back-gate transistor turns on at about 28 volts and the drain-to-source current of the back-gate transistor increases significantly. Consequently, the source 22 is connected by a low impedance channel to the drain 24, even if the intentional front-gate switch function of the exemplary RF CMOS switch 20 is disabled. The second conducting channel for the back-gate transistor (the lower dashed arrow) dramatically reduces the RF isolation of the exemplary RF CMOS switch 20 and the exemplary RF CMOS switch 20 will not work optimally.
Accordingly, there remains a need for improved SOI substrate designs to suppress the back-gate transistors in RF CMOS switches and achieve superior RF isolation performance of the RF CMOS switches.